Silicon wafers of high resistivity produced by the floating zone method (FZ method) have conventionally been used for power devices such as high-voltage power devices and thyristors. However, it is difficult to produce a silicon wafer having a large diameter of 200 mm or more by the FZ method, and the radial resistivity distribution of usual FZ wafers is inferior to that of CZ wafers. Therefore, silicon wafers produced by the CZ method will be promising in the future, because wafers of excellent radial resistivity distribution can be produced by the CZ method, and in addition, wafers of a large size having a diameter of 200 mm or more can sufficiently be produced by the method.
In recent years, in particular, reduction of parasitic capacity is required in semiconductor devices for mobile communications and the latest C-MOS devices. For this reason, a silicon wafer of high resistivity and a large diameter comes to be needed. Moreover, the effect of using a high resistivity substrate on reduction of transmission loss of signals and parasitic capacity in Schottky barrier diodes has been reported. Furthermore, although the so-called SOI (Silicon On Insulator) wafer may be used in order to obtain further higher performance of the aforementioned semiconductor devices, it is required to use a wafer of high resistivity produced by the CZ method as a base wafer even when semiconductor devices are produced by using the SOI wafer in order to obtain a larger diameter of wafer or solve the problem of transmission loss of signals or the like.
However, since the CZ method utilizes a crucible made of quartz, not a small amount of oxygen (interstitial oxygen) is introduced into a silicon crystal. Although each of such oxygen atoms is usually electrically neutral, if they are subjected to a heat treatment at a low temperature of around 350 to 500° C., a plurality of them gather to release electrons and become electrically active oxygen donors. Therefore, if a wafer obtained by the CZ method is subsequently subjected to a heat treatment at about 350 to 500° C. in the device production process and so forth, there arises a problem that resistivity of a high resistivity CZ wafer is reduced due to the formation of the oxygen donors.
In order to prevent the resistivity reduction due to the above oxygen donors and obtain a silicon wafer of high resistivity, methods for producing a silicon single crystal having a low interstitial oxygen concentration from an initial stage of the crystal growth by the magnetic field-applied CZ method (MCZ method) were proposed (refer to Japanese Patent Publication (Kokoku) No. 8-10695 and Japanese Patent Laid-open Publication (Kokai) No. 5-58788). Further, there has also been proposed a method conversely utilizing the phenomenon of the oxygen donor formation, wherein a P-type silicon wafer of a low impurity concentration and low oxygen concentration is subjected to a heat treatment at 400 to 500° C. to generate oxygen donors, and P-type impurities in the P-type silicon wafer is compensated by these oxygen donors so that the wafer should be converted into N-type to produce an N-type silicon wafer of high resistivity (refer to Japanese Patent Publication No. 8-10695).
However, a silicon single crystal of a low interstitial oxygen concentration produced by the MCZ method or the like as mentioned above suffers from a drawback that the density of bulk defects generated by a heat treatment in the device production process becomes low, and thus sufficient gettering effect will be unlikely to be obtained. In devices of a high integration degree, it is essential to impart gettering effect by a certain amount of oxygen precipitation.
Further, the method of obtaining a silicon wafer of N-type by generating oxygen donors by a heat treatment and compensating P-type impurities in the wafer to convert it into N-type is a complicated method that requires a heat treatment for a long period of time. Moreover, this method cannot provide a P-type silicon wafers. In addition, this method also has a drawback that resistivity of wafers obtained by this method may vary depending on a subsequent heat treatment. Furthermore, in this method, in case of high interstitial oxygen concentration, it becomes difficult to control the wafer resistivity. Therefore, this method suffers from a drawback that a low initial concentration of interstitial oxygen in a silicon wafer must be used, and thus the gettering effect of the wafer becomes low.
In order to solve these problems, the applicants of the present application proposed, in a previous application (Japanese Patent Application No. 11-241370, PCT/JP00/01124), a method for producing a silicon wafer, which comprises growing a silicon single crystal ingot having a resistivity of 100 Ω·cm or more and an initial interstitial oxygen concentration of 10 to 25 ppma (JEIDA: Japan Electronic Industry Development Association) by the Czochralski method, processing the silicon single crystal ingot into a wafer, and subjecting the wafer to an oxygen precipitation heat treatment so that a residual interstitial oxygen concentration in the wafer should become 8 ppma or less. According to this method, a CZ wafer of high resistivity of which resistivity is unlikely to decrease even when the wafer is subjected to a heat treatment for device production. Therefore, if this wafer is used as, for example, a base wafer of SOI wafer, devices of extremely high performance for mobile communications can be obtained.
On the other hand, it is considered that, in order to realize a wafer having performance of the same level as the SOI wafer by using a bulk wafer, of which production cost is more inexpensive compared with SOI wafer, so to speak “high resistivity DZ-IG wafer” of a structure having a DZ layer (Denuded Zone layer) sufficiently made defect free on a surface of such a high resistivity CZ wafer is required. Although there has conventionally been the so-called DZ-IG wafer, which is obtained by subjecting a CZ silicon wafer having usual resistivity to a DZ-IG (Intrinsic Gettering) treatment, there has not been conceived to apply this technique to a high resistivity CZ wafer at all. Therefore, the applicant of the present application also disclosed a method for obtaining a high resistivity DZ-IG wafer by a heat treatment that makes the aforementioned interstitial oxygen concentration 8 ppma or less in the previous application (Japanese Patent Application No. 11-241370).
As the DZ-IG treatment applied to a wafer of usual resistivity, a three-step heat treatment is generally used. Supersaturated oxygens in the vicinity of a wafer surface are out-diffused by a first step high temperature heat treatment at 1100° C. or higher, a low temperature heat treatment at around 650° C. is performed as a second step heat treatment to form oxygen precipitation nuclei, and a moderate temperature heat treatment is performed at about 1000° C. as the third step heat treatment to allow growth of the oxide precipitates. By such a three-step heat treatment, an oxide precipitate region is formed in the wafer, and thus a DZ layer in which oxide precipitates do not exist is formed in the vicinity of surface of the front side or back side.
Therefore, the applicants of the present application applied the same heat treatment as the above heat treatment as the heat treatment for obtaining an interstitial oxygen concentration of 8 ppma or less. As a result, it was found that a high resistivity DZ-IG wafer having a high resistivity of 100 Ω·cm or more and having a DZ layer free from crystal defects near the surface and an oxide precipitate layer in which oxide precipitates are sufficiently precipitated could be obtained.
It was considered that such a high resistivity DZ-IG wafer could sufficiently serve as an alternative of SOI wafers for mobile communications. However, subsequent investigations revealed that, if such a DZ-IG wafer was subjected to a heat treatment during the device production process, the resistivity near the wafer surface was extremely reduced as the case may be, and thus sufficient high resistivity may not be obtained.
Further, it was also found that, although the DZ layer formed by such a heat treatment was surely made defect free as for defects originated from oxide precipitates, grown-in defects called COP (Crystal Originated Particle) were not eliminated and still remained.
COP is a void of 0.1 μm order size formed by aggregation of excessive vacancies during the growth of CZ silicon single crystals, and the internal surface thereof is covered with a thin oxide film. Further, it is known that, if a device is formed on a portion where such grown-in defects exist, device characteristics such as oxide dielectric breakdown voltage are degraded.